Developing state of the art products and patents, leveraging extensive experience in IC design. The most noteworthy achievement is the co-invention of the ultra-low power CoolRunner CPLD family, which produced hundreds of implementations and a peak annual sales of $200M in 2010.

Key Hardware and Product Development Skills  
  1. Custom IC Research, Development & Design
  1. Deep sub-micron CMOS (28nm +)
  1. HSPICE, HSIM and Simulation Tools
  1. Design Experience: Custom CMOS IC design, EEPROM, CMOS RAM, ESD, Latch-up, Multipliers, and Adders 
Key Software Proficiencies
  1. Cadence tool suite including: Virtuoso, 
    Analog Artist, and Layout
  1. Caliber LVS, DRC, RCX

Summary of Experience
Xilinx, Inc., Albuquerque, NM
1999-2011
Senior Staff IC Design Engineer/ Engineering Manager
  1. IC Design for all CoolRunner devices.
  1. Designed the nonvolatile memory, high voltage programming circuitry and configuration circuitry for the CoolRunner CPLD product. 
  1. Managed a team of 4 Engineers and 2 Layout Designers.
  2. Established co-op engineering program with 14 students completing the program over 10 years.
  3. Designed global clock tree for all Spartan FPGA devices.
  4. Responsible for hclk and vframe for Vertex FPGA devices.
Philips Semiconductor, Albuquerque, NM
1994-1999
Senior Staff / Staff IC Design Engineer
  1. Co-invented and designed the CoolRunner CPLD Family. (0.5um EE CMOS process).
  2. Designed and developed the nonvolatile memory, configuration and in-circuit programming.
  3. Worked 6 months at Philips Nat lab Eindhoven, The Netherlands developing of test vehicle for next generation CMOS nonvolatile process.

Lattice Semiconductor, Hillsboro, OR
1991-1994
Senior Design Engineer
  1. Designed EEPROM based programmable logic devices.
  2. Designed and developed a programmable CMOS Cross Point switch.
  3. Designed speed and technology upgraded product and Lattice’s first 3v product.

Philips Research Lab., Eindhoven, The Netherlands
1985-1990
Contract Design and Product Engineer
  1. Member of the Advanced Memory Design Team.
  1. Designed and developed sub micron SRAM products for the MEGA project.
  1. Designed the I/O circuitry, address detection, and equalization circuitry for the 256Kx1 CMOS SRAM. 
  1. This design was developed as a high speed memory product used as the technology driver for the MEGA project. 
Education
Bachelor of Science in Electrical Engineering
University of Michigan Dearborn
United States Patents 
  1. Xilinx, Inc.: 6,842,041; 5,684,413; 5,889,412; 7,746,699; 7,536,559; 7,023,744; 6,963,222; 7,016,219; 6,838,924;6,714,041; 6,717,859; 6,590,416; 6,603,331
  2. Philips Semiconductor: 6,448,845; 5,265,064; 6,108,257; 6,038,194; 5,087,840; 4,929,911; 5,224,071; 4,951,254;5,889,412; 5,033,024; 5,212,413; 5,040,152; 4,931,667
  3. Lattice Semiconductor: 5,452,229
Awards
  1. EDN Innovation of the Year (1996) for CoolRunner CPLD Invention, Design and Development
  2. EDN Innovator of the Year (1996) Finalist for CoolRunner CPLD Invention, Design and Development